We changed our HW definition to make that a GPIO, and we take it out of reset in the early board init function of u-boot. Have you tried with slightly rearranged device tree like this? I enable eth0 and see transactions on the MDIO bus. Again, this appears to be a software issue. There was a fix in the emac drivers, but it’s not being used anymore.
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Check the reset pin to the PHYs.
Flipping bit 1 would translate the address of the two PHYs to 2 and 3 instead of 0 and 1. We have detected your current browser version is not the latest one.
It will be fixed in the We are not able to run our dual GEM config. FYI, Tool and Software tags: With linux this indeed is a problem, when doing it correctly in devicetree then lots of errors come during boot, claiming PHY 0 is invalid, then PHY 0 is enabled, and working, and the second PHY with address 1 valid address remains not configured and is pny not accessible.
Solved: Dual Marvell 88e PHY Ethernet problem – Xilinx – Community Forums
Reluctant to pursue it as we are not using Petalinux:. Note that it assigns a different MAC address than is assinged in the device tree file. Yes, I have tried it, but eth1 still doesn’t work. Thanks for the information.
net: phy: marvell: fix Marvell 88E1512 used in SGMII mode [Linux 4.9.36]
Pyy looking for some insight that I’m missing, or some other clue to indicate why the kernel drivers can’t detect PHY1 at address 1 correctly.
Another question if I may, what about the dsa part in the tree, isn’t it required?
I recommend the device tree in the answer with any necessary modifications for your implementation. I have tried the current xilinx-linux git repo, and the patch is not in that repo, nor is the patch applicable to that repo. So I would suggest marvll to try testing the setup in Give Kudos to a post which you think is helpful and reply oriented. I’ll update you when I have more information.
The software doesn’t seem to do anything with it. Verified fix for this problem. Please upgrade to a Xilinx.
net: phy: marvell: fix Marvell 88E used in SGMII mode [Linux ] – Linux Kernels
Hope this helps everyone with this problem ChromeFirefoxInternet Explorer 11Safari. It’s likely that a hardware workaround in the fabric is easier to implement than phyy into the Linux core software. Build the device tree blob, and copy uImage and the. It’s almost as if the default config of the PHY is enough to pass data to the eth1 interface even though it hasn’t been configured.
I had seen that, but we run both PHYs a 1. It will doubtless require changes to the linux driver stack to get it working. We have a custom board with a Zynq using two Marvell 88e PHYs for dual ethernet and have not been able to get eth1 up and running on linu eth0 works fine. Add mdio in the top level: What other kernel settings did you have to enable to allow the Marvell 88e PHY to have the correct drivers from petalinux?
If they both operate at 2. All forum topics Previous Topic Next Topic. The state machine for this is pretty simple and basically counts the bits as they go out and just inverts the value for one bit period during the desired address bit for example bit 1.
I have tried that previously and once againt to verify. Anyone else had it work?
If they both operate at 3.